1. Field of the Invention
The present invention relates to an image pickup apparatus for picking up an image of an object.
2. Related Background Art
In recent years, for the promotion of high resolution, the cell size reduction of photoelectric conversion devices employing the miniaturization process has been vigorously carried out, while an amplification type solid-state image pickup device which is capable of amplifying a photoelectric conversion signal to output the resultant signal thus amplified has received much attention in order to avoid the reduction in magnitude of photoelectric conversion output signals or the like due to the miniaturization process.
As for such amplification type solid-state image pickup devices, there are devices of a MOS type, an AMI type, a CMD type, a BASIS type, and the like. Of those, the MOS type solid-state image pickup device is constructed such that optical carriers generated in a photodiode are accumulated in a gate electrode of a MOS transistor, and in accordance with the driving timing provided from a scanning circuit, the potential change thereof is amplified in terms of the electric charges to be outputted to an output unit.
Of the MOS type solid-state image pickup devices, a CMOS type solid-state image pickup device which, including its peripheral circuit unit, is wholly realized through the CMOS process has especially received attention.
FIG. 5 is an equivalent circuit diagram of a conventional CMOS solid-state image pickup device. FIG. 7 is a schematic mounting plan view of horizontal transfer switches N511 to N513, a reset switch N514, a horizontal scanning circuit block 5, and a differential amplifier circuit 51 shown in FIG. 5. By the way, FIG. 7 shows the situation in which the above-mentioned constituent elements are connected to one another through two wiring layers consisting of a first wiring layer and a second wiring layer.
The CMOS type solid-state image pickup device shown in FIG. 5 includes a pixel unit 1, a vertical scanning circuit block 2, a horizontal scanning circuit block 5, an input MOS transistor N51, load MOS transistors N52 to N54, clamp capacitors C01 to C03, clamp switches N55 to N57, transfer switches N58 to N510, signal holding (storage) capacitors CT1 to CT3, horizontal transfer switches N511 to N513, a reset switch N514, and the differential amplifier circuit 51 all of which will be described hereinbelow.
Photodiodes D11 to D33 provided in the pixel unit 1 generate optical signal electric charges. In this case, the anode sides of the photodiodes D11 to D33 are grounded. The cathode sides of the photodiodes D11 to D33 are respectively connected to gates of amplification MOS transistors M311 to M333 through transfer MOS transistors M111 to M133.
In addition, to the gates of the amplification MOS transistors M311 to M333, sources of reset MOS transistors M211 to M233 for reset of these gates are respectively connected. Drains of the reset MOS transistors M211 to M233 are connected to a reset power source.
Furthermore, drains of the amplification MOS transistors M311 to M333 are connected to a power source and sources thereof are respectively connected to drains of selection MOS transistors M411 to M433. A gate of the transfer MOS transistor M111 is connected to a first row selection line (vertical scanning line) PTX1 which is arranged so as to extend transversely.
Gates of the similar transfer MOS transistors M121 and M131 of other pixel cells which are arranged in the same row are also commonly connected to the first row selection line PTX1. A gate of the MOS transistor M211 is connected to a second row selection line (vertical scanning line) PRES1 which is arranged so as to extend transversely.
Gates of the similar reset MOS transistors M221 and M231 of other pixel cells which are arranged in the same row are also commonly connected to the second row selection line PRES1. A gate of the selection MOS transistor M411 is connected to a third row selection line (vertical scanning line) PSEL1 which is arranged so as to extend transversely.
Gates of the similar selection MOS transistors M421 and M431 of other pixel cells which are arranged in the same row are also commonly connected to the third row selection line PSEL1. The first to third row selection lines are connected to the vertical scanning circuit block 2, and a signal voltage is supplied thereto on the basis of the operating timing which will be described later.
In the remaining rows shown in FIG. 5, the pixel cells having the same structure and the row selection lines are provided. PTX2 and PTX3, PRES2 and PRES3, and PSEL2 and PSEL3 which are formed in the vertical scanning circuit block 2 are supplied to these row selection lines. A source of the selection MOS transistor M411 is connected to a vertical signal line V1 which is arranged so as to extend longitudinally.
Sources of the similar selection MOS transistors M412 and M413 of the pixel cells which are arranged in the same row are also connected to the vertical signal line V1. The vertical signal line V1 is connected to a load MOS transistor N52 as load means.
Likewise, the selection MOS transistors and the load MOS transistors are connected to the remaining vertical signal lines V2 and V3 shown in FIG. 5.
Furthermore, sources of the load MOS transistors N52 to N54 are connected to a common GND line 4, and gates thereof are commonly connected to both of a gate and a drain of the input MOS transistor N51 and also are coupled to a voltage input terminal Vbias.
The vertical signal line V1 is connected to a capacitor CT1 for temporarily holding a signal through the clamp capacitor C01 and the transfer switch N58, and also is connected to an inverting input terminal (horizontal output line) of the differential amplifier circuit 51 through the horizontal transfer switch N511.
A non-inverting input terminal and an inverting input terminal of the differential amplifier circuit 51 are respectively coupled to a reset voltage Vres of the horizontal output line and a reset voltage Vres of the horizontal output line through the reset switch N514. The other terminal of the signal holding capacitor CT1 is grounded.
A junction point between the clamp capacitor C01 and the transfer switch N58 is connected to a clamp power source through the clamp switch N55. A gate of the horizontal transfer switch N511 is connected to a signal line H1 and the horizontal scanning circuit block 5.
The reading-out circuits having the same configuration are respectively provided in the remaining columns V2 and V3 shown in FIG. 5. In addition, gates of the clamp switches N55 to N57 which are connected to the respective columns and gates of the transfer switches N58 to N510 which are connected to the respective columns are commonly connected to a clamp signal input terminal PCOR and a transfer signal input terminal PT, respectively, and the signal voltages are respectively supplied thereto on the basis of the operating timing as will be described later.
FIG. 6 is a timing chart useful in explaining the operation of the CMOS type solid-state image pickup device shown in FIG. 5. Prior to the operation for reading out the optical signal electric charges from the photodiodes D11 to D33, the levels at the gates PRES1 of the reset MOS transistors M211 to M231 go high.
As a result, the gates of the amplification MOS transistors M311 to M331 are reset to the reset power source. After the levels at the gates PCOR of the clamp switches N55 to N57 go high at the same time as the levels at the gates PRES1 of the reset MOS transistors M211 to M231 return back to the low level, the levels at the gates PSEL1 of the selection MOS transistors M411 to M431 go high.
As a result, a reset signal (noise signal) on which the reset noise is superimposed is read out to the vertical signal lines V1 to V3 to be clamped in the clamp capacitors C01 to C03. At the same time, the levels at the gates PT of the transfer switches N58 to N510 go high and the signal holding capacitors CT1 to CT3 are reset to a clamp voltage.
Next, the levels at the gates PCOR of the clamp switches N55 to N57 return back to the low level. Next the levels at the gates PTX1 of the transfer MOS transistors M111 to M131 go high, and an optical signal is read out to the vertical signal lines V1 to V3 at the same time as the optical signal electric charges of the photodiodes D11 to D31 are transferred to the gates of the amplification MOS transistors M311 to M331.
Next, after the levels at the gates PTX1 of the transfer MOS transistors M111 to M131 have returned back to the low level, the levels at the gates PT of the transfer switches N58 to N510 go low. As a result, a signal corresponding to change (optical signal) from the reset signal is read out to the signal holding capacitors CT1 to CT3.
In the operation up to here, the optical signals of the pixel cells connected to the first row are respectively held in the signal holding capacitors CT1 to CT3 connected to the respective columns.
Next, the levels at the gates PRES1 of the reset MOS transistors M211 to M231 and the levels at the gates PTX1 of the transfer MOS transistors M111 to M131 go high, and the optical signal electric charges of the photodiodes D11 to D31 are reset.
Thereafter, the levels at the gates of the horizontal transfer switches N511 to N513 in the respective columns successively go high with the signals which are supplied from the horizontal scanning circuit block 5 to be transmitted through the signal lines H1 to H3, and the voltages which are respectively held in the signal holding capacitors CT1 to CT3 are successively read out to the horizontal output line to be successively outputted to the output terminal OUT.
The horizontal output line is reset to a reset voltage Vres with the reset switch N514 between reading-out operations of the signals in the columns. Thus, the operation for reading out the signals of the pixel cells connected to the first row is completed. Likewise, the signals of the pixel cells connected to the rows in and after the second row are successively read out with the signals from the vertical scanning circuit block to complete the operation for reading out the signals of all of the pixel cells.
However, in the prior art, the horizontal output line to which the sources of the horizontal transfer switches N511 to N513 are commonly connected is capacitively coupled to the signal lines H1 to H3 for driving of the gate terminals through the gate-to-source capacitors of the horizontal transfer switches N511 to N513.
In addition, the horizontal output line overlaps the wiring of the signal lines H1 to H3 from the horizontal scanning circuit block 5 to be capacitively coupled thereto. The signals passing through the signal lines H1 to H3 are supplied from the power source of the horizontal scanning circuit block 5 and GND, and as a result the horizontal output line is capacitively coupled to the power source of the horizontal scanning circuit block 5 and GND.
Furthermore, the wiring of the horizontal output line is provided above a semiconductor substrate and hence is also capacitively coupled to the semiconductor substrate. As in the driving method described with reference to FIG. 6, the inverting input terminal of the differential amplifier circuit 51 is in the state of high impedance (floating) at the timing when the signal is read out to the horizontal output line, and hence is easily affected by the disturbance noise generated due to the capacitive coupling.
In general, in many cases, the power source for the horizontal scanning circuit block 5 and GND have the spike-like noise superimposed thereon due to the influence of the through current in a digital circuit or the like. Thus, this noise exerts an influence on the horizontal output line. As a result, there is encountered the problem that the noise exerts an influence on an output waveform (sensor output waveform) of the differential amplifier circuit 51 so that it is impossible to obtain the essential image of an object.